diff options
| author | Joshua Yun <jjyun4@illinois.edu> | 2023-08-28 14:42:23 -0500 |
|---|---|---|
| committer | Joshua Yun <jjyun4@illinois.edu> | 2023-08-28 14:42:23 -0500 |
| commit | c1fa3c36da28e9e947f6279329c47777f31fe7a2 (patch) | |
| tree | bd321c8e33200427b23bffe96c7c1bae90d8a044 /verilog/tbalu.h | |
| parent | d069ea63cce08c0f5c8d7da7f8ab05115bd8d856 (diff) | |
| download | riscv-processor-inorder-c1fa3c36da28e9e947f6279329c47777f31fe7a2.tar.gz | |
Diffstat (limited to 'verilog/tbalu.h')
| -rw-r--r-- | verilog/tbalu.h | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/verilog/tbalu.h b/verilog/tbalu.h new file mode 100644 index 0000000..9e010e6 --- /dev/null +++ b/verilog/tbalu.h @@ -0,0 +1,15 @@ +#ifndef ALUOP +#define ALUOP + +#define ADD 0b0000 +#define SUB 0b1000 +#define XOR 0b0010 +#define OR 0b0110 +#define AND 0b0111 +#define SLL 0b0001 +#define SRL 0b0101 +#define SRA 0b1101 +#define SLT 0b0010 +#define SLTU 0b0011 + +#endif |