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authorjoshua <joshua@joshuayun.com>2023-12-30 23:54:31 -0500
committerjoshua <joshua@joshuayun.com>2023-12-30 23:54:31 -0500
commit86608c6770cf08c138a2bdab5855072f64be09ef (patch)
tree494a61b3ef37e76f9235a0d10f5c93d97290a35f /Core/Inc/Si5351A-RevB-Registers.h
downloadsdr-software-master.tar.gz
initial commitHEADmaster
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+/*
+ * Si5351A Rev B Configuration Register Export Header File
+ *
+ * This file represents a series of Skyworks Si5351A Rev B
+ * register writes that can be performed to load a single configuration
+ * on a device. It was created by a Skyworks ClockBuilder Pro
+ * export tool.
+ *
+ * Part: Si5351A Rev B
+ * Design ID:
+ * Includes Pre/Post Download Control Register Writes: Yes
+ * Created By: ClockBuilder Pro v4.11.0.1 [2023-09-14]
+ * Timestamp: 2023-12-05 04:14:31 GMT-06:00
+ *
+ * A complete design report corresponding to this export is included at the end
+ * of this header file.
+ *
+ */
+
+#ifndef SI5351A_REVB_REG_CONFIG_HEADER
+#define SI5351A_REVB_REG_CONFIG_HEADER
+
+#define SI5351A_REVB_REG_CONFIG_NUM_REGS 61
+
+typedef struct
+{
+ uint8_t address; /* 16-bit register address */
+ uint8_t value; /* 8-bit register data */
+
+} si5351a_revb_register_t;
+
+si5351a_revb_register_t const si5351a_revb_registers[SI5351A_REVB_REG_CONFIG_NUM_REGS] =
+{
+ { 0x02, 0x53 },
+ { 0x03, 0x00 },
+ { 0x04, 0x20 },
+ { 0x07, 0x00 },
+ { 0x0F, 0x00 },
+ { 0x10, 0x0F },
+ { 0x11, 0x0F },
+ { 0x12, 0x0F },
+ { 0x13, 0x8C },
+ { 0x14, 0x8C },
+ { 0x15, 0x8C },
+ { 0x16, 0x8C },
+ { 0x17, 0x8C },
+ { 0x1A, 0x00 },
+ { 0x1B, 0x01 },
+ { 0x1C, 0x00 },
+ { 0x1D, 0x10 },
+ { 0x1E, 0x00 },
+ { 0x1F, 0x00 },
+ { 0x20, 0x00 },
+ { 0x21, 0x00 },
+ { 0x2A, 0x00 },
+ { 0x2B, 0x01 },
+ { 0x2C, 0x00 },
+ { 0x2D, 0x0D },
+ { 0x2E, 0x00 },
+ { 0x2F, 0x00 },
+ { 0x30, 0x00 },
+ { 0x31, 0x00 },
+ { 0x32, 0x00 },
+ { 0x33, 0x04 },
+ { 0x34, 0x62 },
+ { 0x35, 0xBD },
+ { 0x36, 0x20 },
+ { 0x37, 0x00 },
+ { 0x38, 0x00 },
+ { 0x39, 0x00 },
+ { 0x3A, 0x00 },
+ { 0x3B, 0x04 },
+ { 0x3C, 0x62 },
+ { 0x3D, 0xBD },
+ { 0x3E, 0x20 },
+ { 0x3F, 0x00 },
+ { 0x40, 0x00 },
+ { 0x41, 0x00 },
+ { 0x5A, 0x00 },
+ { 0x5B, 0x00 },
+ { 0x95, 0x00 },
+ { 0x96, 0x00 },
+ { 0x97, 0x00 },
+ { 0x98, 0x00 },
+ { 0x99, 0x00 },
+ { 0x9A, 0x00 },
+ { 0x9B, 0x00 },
+ { 0xA2, 0x00 },
+ { 0xA3, 0x00 },
+ { 0xA4, 0x00 },
+ { 0xA5, 0x00 },
+ { 0xA6, 0x00 },
+ { 0xA7, 0x00 },
+ { 0xB7, 0xD2 },
+
+};
+
+/*
+ * Design Report
+ *
+ * Overview
+ * ========
+ *
+ * Part: Si5351A
+ * Project File: C:\Users\ldu08\Downloads\Si5351A-RevB-Project.slabtimeproj
+ * Created By: ClockBuilder Pro v4.11.0.1 [2023-09-14]
+ * Timestamp: 2023-12-05 04:14:31 GMT-06:00
+ *
+ * Design Rule Check
+ * =================
+ *
+ * Errors:
+ * - No errors
+ *
+ * Warnings:
+ * - No warnings
+ *
+ * Design
+ * ======
+ * I2C Address: 0x60
+ *
+ * Inputs:
+ * IN0: 25 MHz
+ *
+ * Outputs:
+ * OUT0: 30 MHz
+ * Enabled LVCMOS 8 mA
+ * Offset 0.000 s
+ * OUT1: 10 kHz
+ * Enabled LVCMOS 8 mA
+ * Offset 0.000 s
+ * OUT2: 10 kHz
+ * Enabled LVCMOS 8 mA
+ * Offset 0.000 s
+ *
+ * Frequency Plan
+ * ==============
+ *
+ * PLL_A:
+ * Enabled Features = None
+ * Fvco = 900 MHz
+ * M = 36
+ * Input0:
+ * Source = Crystal
+ * Source Frequency = 25 MHz
+ * Fpfd = 25 MHz
+ * Load Capacitance = Load_10pF
+ * Output0:
+ * Features = None
+ * Disabled State = StopLow
+ * R = 1 (2^0)
+ * Fout = 30 MHz
+ * N = 30
+ * Output1:
+ * Features = None
+ * Disabled State = StopLow
+ * R = 64 (2^6)
+ * Fout = 10 kHz
+ * N = 1406.25
+ * Output2:
+ * Features = None
+ * Disabled State = StopLow
+ * R = 64 (2^6)
+ * Fout = 10 kHz
+ * N = 1406.25
+ *
+ * Settings
+ * ========
+ *
+ * Location Setting Name Decimal Value Hex Value
+ * ------------ -------------- ----------------- -----------------
+ * 0x0002[3] XO_LOS_MASK 0 0x0
+ * 0x0002[4] CLK_LOS_MASK 1 0x1
+ * 0x0002[5] LOL_A_MASK 0 0x0
+ * 0x0002[6] LOL_B_MASK 1 0x1
+ * 0x0002[7] SYS_INIT_MASK 0 0x0
+ * 0x0003[7:0] CLK_OEB 0 0x00
+ * 0x0004[4] DIS_RESET_LOLA 0 0x0
+ * 0x0004[5] DIS_RESET_LOLB 1 0x1
+ * 0x0007[7:4] I2C_ADDR_CTRL 0 0x0
+ * 0x000F[2] PLLA_SRC 0 0x0
+ * 0x000F[3] PLLB_SRC 0 0x0
+ * 0x000F[4] PLLA_INSELB 0 0x0
+ * 0x000F[5] PLLB_INSELB 0 0x0
+ * 0x000F[7:6] CLKIN_DIV 0 0x0
+ * 0x0010[1:0] CLK0_IDRV 3 0x3
+ * 0x0010[3:2] CLK0_SRC 3 0x3
+ * 0x0010[4] CLK0_INV 0 0x0
+ * 0x0010[5] MS0_SRC 0 0x0
+ * 0x0010[6] MS0_INT 0 0x0
+ * 0x0010[7] CLK0_PDN 0 0x0
+ * 0x0011[1:0] CLK1_IDRV 3 0x3
+ * 0x0011[3:2] CLK1_SRC 3 0x3
+ * 0x0011[4] CLK1_INV 0 0x0
+ * 0x0011[5] MS1_SRC 0 0x0
+ * 0x0011[6] MS1_INT 0 0x0
+ * 0x0011[7] CLK1_PDN 0 0x0
+ * 0x0012[1:0] CLK2_IDRV 3 0x3
+ * 0x0012[3:2] CLK2_SRC 3 0x3
+ * 0x0012[4] CLK2_INV 0 0x0
+ * 0x0012[5] MS2_SRC 0 0x0
+ * 0x0012[6] MS2_INT 0 0x0
+ * 0x0012[7] CLK2_PDN 0 0x0
+ * 0x0013[1:0] CLK3_IDRV 0 0x0
+ * 0x0013[3:2] CLK3_SRC 3 0x3
+ * 0x0013[4] CLK3_INV 0 0x0
+ * 0x0013[5] MS3_SRC 0 0x0
+ * 0x0013[6] MS3_INT 0 0x0
+ * 0x0013[7] CLK3_PDN 1 0x1
+ * 0x0014[1:0] CLK4_IDRV 0 0x0
+ * 0x0014[3:2] CLK4_SRC 3 0x3
+ * 0x0014[4] CLK4_INV 0 0x0
+ * 0x0014[5] MS4_SRC 0 0x0
+ * 0x0014[6] MS4_INT 0 0x0
+ * 0x0014[7] CLK4_PDN 1 0x1
+ * 0x0015[1:0] CLK5_IDRV 0 0x0
+ * 0x0015[3:2] CLK5_SRC 3 0x3
+ * 0x0015[4] CLK5_INV 0 0x0
+ * 0x0015[5] MS5_SRC 0 0x0
+ * 0x0015[6] MS5_INT 0 0x0
+ * 0x0015[7] CLK5_PDN 1 0x1
+ * 0x0016[1:0] CLK6_IDRV 0 0x0
+ * 0x0016[3:2] CLK6_SRC 3 0x3
+ * 0x0016[4] CLK6_INV 0 0x0
+ * 0x0016[5] MS6_SRC 0 0x0
+ * 0x0016[6] FBA_INT 0 0x0
+ * 0x0016[7] CLK6_PDN 1 0x1
+ * 0x0017[1:0] CLK7_IDRV 0 0x0
+ * 0x0017[3:2] CLK7_SRC 3 0x3
+ * 0x0017[4] CLK7_INV 0 0x0
+ * 0x0017[5] MS7_SRC 0 0x0
+ * 0x0017[6] FBB_INT 0 0x0
+ * 0x0017[7] CLK7_PDN 1 0x1
+ * 0x001C[17:0] MSNA_P1 4096 0x01000
+ * 0x001F[19:0] MSNA_P2 0 0x00000
+ * 0x001F[23:4] MSNA_P3 1 0x00001
+ * 0x002C[17:0] MS0_P1 3328 0x00D00
+ * 0x002F[19:0] MS0_P2 0 0x00000
+ * 0x002F[23:4] MS0_P4 1 0x00001
+ * 0x0034[17:0] MS1_P1 179488 0x2BD20
+ * 0x0034[6:4] R1_DIV 6 0x6
+ * 0x0037[19:0] MS1_P2 0 0x00000
+ * 0x0037[23:4] MS1_P4 4 0x00004
+ * 0x003C[17:0] MS2_P1 179488 0x2BD20
+ * 0x003C[6:4] R2_DIV 6 0x6
+ * 0x003F[19:0] MS2_P2 0 0x00000
+ * 0x003F[23:4] MS2_P4 4 0x00004
+ * 0x005A[7:0] MS6_P2 0 0x00
+ * 0x005B[7:0] MS7_P2 0 0x00
+ * 0x0095[14:0] SSDN_P2 0 0x0000
+ * 0x0095[7] SSC_EN 0 0x0
+ * 0x0097[14:0] SSDN_P3 0 0x0000
+ * 0x0097[7] SSC_MODE 0 0x0
+ * 0x0099[11:0] SSDN_P1 0 0x000
+ * 0x009A[15:4] SSUDP 0 0x000
+ * 0x00A2[21:0] VCXO_PARAM 0 0x000000
+ * 0x00A5[7:0] CLK0_PHOFF 0 0x00
+ * 0x00A6[7:0] CLK1_PHOFF 0 0x00
+ * 0x00A7[7:0] CLK2_PHOFF 0 0x00
+ * 0x00B7[7:6] XTAL_CL 3 0x3
+ *
+ *
+ */
+
+#endif \ No newline at end of file
generated by cgit v1.2.3 (git 2.39.1) at 2024-09-19 22:21:44 +0000