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authorJoshua Yun <jjyun4@illinois.edu>2023-08-28 14:42:23 -0500
committerJoshua Yun <jjyun4@illinois.edu>2023-08-28 14:42:23 -0500
commitc1fa3c36da28e9e947f6279329c47777f31fe7a2 (patch)
treebd321c8e33200427b23bffe96c7c1bae90d8a044 /verilog/Makefile
parentd069ea63cce08c0f5c8d7da7f8ab05115bd8d856 (diff)
downloadriscv-processor-inorder-master.tar.gz
Added new riscv processor design into git repoHEADmaster
Diffstat (limited to 'verilog/Makefile')
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1 files changed, 10 insertions, 0 deletions
diff --git a/verilog/Makefile b/verilog/Makefile
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+datapath_test:
+ verilator --trace --cc --exe --build -j 0 -Wall tbdatapath.cpp datapath.v
+ ./obj_dir/Vdatapath
+datapath_synth:
+ yosys -p "read_verilog datapath.v ; hierarchy -top datapath -libdir . ; synth_ecp5"
+clean:
+ rm -rf log_* obj_dir
+alu_test:
+ verilator --cc --exe --build -j 0 -Wall tbalu.cpp alu.v
+ ./obj_dir/Valu