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| author | joshua <joshua@fedora.framework> | 2022-05-14 23:30:38 -0500 |
|---|---|---|
| committer | joshua <joshua@fedora.framework> | 2022-05-14 23:30:38 -0500 |
| commit | b8936029065835366e9e057a219c0c5194db8662 (patch) | |
| tree | 31e50944ac6e23850f92bb0e0f6d851b74307f60 /verilog/alu/aluOp.vh | |
| parent | d6b7d26cf51b4b3a7b5604f9b81bb43f55cbc33c (diff) | |
| download | riscv-processor-inorder-b8936029065835366e9e057a219c0c5194db8662.tar.gz | |
Verilog update
Diffstat (limited to 'verilog/alu/aluOp.vh')
| -rw-r--r-- | verilog/alu/aluOp.vh | 14 |
1 files changed, 0 insertions, 14 deletions
diff --git a/verilog/alu/aluOp.vh b/verilog/alu/aluOp.vh deleted file mode 100644 index c67cd33..0000000 --- a/verilog/alu/aluOp.vh +++ /dev/null @@ -1,14 +0,0 @@ -`ifndef ALU_OP -`define ALU_OP -`define ADD 4'b0000 -`define SUB 4'b1000 -`define XOR 4'b0100 -`define OR 4'b0110 -`define AND 4'b0111 -`define SLL 4'b0001 -`define SRL 4'b0101 -`define SRA 4'b1101 -`define SLT 4'b0010 -`define SLTU 4'b0011 -`define NONE 4'h1111 -`endif |