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author | joshua <joshua@joshuayun.com> | 2022-05-16 11:02:27 -0400 |
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committer | joshua <joshua@joshuayun.com> | 2022-05-16 11:02:27 -0400 |
commit | 18d1ae8dd266a6aa126479a742e0e6f257d5f8a9 (patch) | |
tree | c18f3db13e81644ed7cf6530328c0bebaf0b234a /verilog/alu/v6/obj_dir/Valu6__Syms.cpp | |
parent | 7a8afb2b6659f88881139fcbcb02de5476952152 (diff) | |
download | riscv-processor-inorder-18d1ae8dd266a6aa126479a742e0e6f257d5f8a9.tar.gz |
revised gitignore
Diffstat (limited to 'verilog/alu/v6/obj_dir/Valu6__Syms.cpp')
-rw-r--r-- | verilog/alu/v6/obj_dir/Valu6__Syms.cpp | 26 |
1 files changed, 0 insertions, 26 deletions
diff --git a/verilog/alu/v6/obj_dir/Valu6__Syms.cpp b/verilog/alu/v6/obj_dir/Valu6__Syms.cpp deleted file mode 100644 index fe8a162..0000000 --- a/verilog/alu/v6/obj_dir/Valu6__Syms.cpp +++ /dev/null @@ -1,26 +0,0 @@ -// Verilated -*- C++ -*- -// DESCRIPTION: Verilator output: Symbol table implementation internals - -#include "Valu6__Syms.h" -#include "Valu6.h" -#include "Valu6___024root.h" - -// FUNCTIONS -Valu6__Syms::~Valu6__Syms() -{ -} - -Valu6__Syms::Valu6__Syms(VerilatedContext* contextp, const char* namep,Valu6* modelp) - : VerilatedSyms{contextp} - // Setup internal state of the Syms class - , __Vm_modelp{modelp} - // Setup module instances - , TOP{this, namep} -{ - // Configure time unit / time precision - _vm_contextp__->timeunit(-6); - _vm_contextp__->timeprecision(-9); - // Setup each module's pointers to their submodules - // Setup each module's pointer back to symbol table (for public functions) - TOP.__Vconfigure(true); -} |