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author | joshua <joshua@joshuayun.com> | 2022-05-16 11:00:23 -0400 |
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committer | joshua <joshua@joshuayun.com> | 2022-05-16 11:00:23 -0400 |
commit | 7a8afb2b6659f88881139fcbcb02de5476952152 (patch) | |
tree | 446ca228be5746e0b6af24f44072a42289c13899 /verilog/alu/v6/obj_dir/Valu6___024root.h | |
parent | b8936029065835366e9e057a219c0c5194db8662 (diff) | |
download | riscv-processor-inorder-7a8afb2b6659f88881139fcbcb02de5476952152.tar.gz |
Yes
Diffstat (limited to 'verilog/alu/v6/obj_dir/Valu6___024root.h')
-rw-r--r-- | verilog/alu/v6/obj_dir/Valu6___024root.h | 8 |
1 files changed, 3 insertions, 5 deletions
diff --git a/verilog/alu/v6/obj_dir/Valu6___024root.h b/verilog/alu/v6/obj_dir/Valu6___024root.h index f568bf9..968e6b6 100644 --- a/verilog/alu/v6/obj_dir/Valu6___024root.h +++ b/verilog/alu/v6/obj_dir/Valu6___024root.h @@ -13,23 +13,21 @@ VL_MODULE(Valu6___024root) { // DESIGN SPECIFIC STATE VL_IN8(alu_op_i,3,0); - VL_OUT8(debugop,3,0); VL_IN(alu_in_1,31,0); VL_IN(alu_in_2,31,0); VL_OUT(alu_output,31,0); - VL_OUT(debugsum,31,0); IData/*31:0*/ alu6__DOT__sum; // INTERNAL VARIABLES - Valu6__Syms* vlSymsp; // Symbol table + Valu6__Syms* const vlSymsp; // CONSTRUCTORS - Valu6___024root(const char* name); + Valu6___024root(Valu6__Syms* symsp, const char* name); ~Valu6___024root(); VL_UNCOPYABLE(Valu6___024root); // INTERNAL METHODS - void __Vconfigure(Valu6__Syms* symsp, bool first); + void __Vconfigure(bool first); } VL_ATTR_ALIGNED(VL_CACHE_LINE_BYTES); |