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| author | joshua <joshua@joshuayun.com> | 2022-05-16 11:00:23 -0400 |
|---|---|---|
| committer | joshua <joshua@joshuayun.com> | 2022-05-16 11:00:23 -0400 |
| commit | 7a8afb2b6659f88881139fcbcb02de5476952152 (patch) | |
| tree | 446ca228be5746e0b6af24f44072a42289c13899 /verilog/alu/v6 | |
| parent | b8936029065835366e9e057a219c0c5194db8662 (diff) | |
| download | riscv-processor-inorder-7a8afb2b6659f88881139fcbcb02de5476952152.tar.gz | |
Yes
Diffstat (limited to 'verilog/alu/v6')
25 files changed, 1132 insertions, 2725 deletions
diff --git a/verilog/alu/v6/obj_dir/Valu6 b/verilog/alu/v6/obj_dir/Valu6 Binary files differindex 1614e40..9c3d7d9 100755 --- a/verilog/alu/v6/obj_dir/Valu6 +++ b/verilog/alu/v6/obj_dir/Valu6 diff --git a/verilog/alu/v6/obj_dir/Valu6.cpp b/verilog/alu/v6/obj_dir/Valu6.cpp index 2e02259..75840d5 100644 --- a/verilog/alu/v6/obj_dir/Valu6.cpp +++ b/verilog/alu/v6/obj_dir/Valu6.cpp @@ -1,207 +1,118 @@ // Verilated -*- C++ -*- -// DESCRIPTION: Verilator output: Design implementation internals -// See Valu6.h for the primary calling header +// DESCRIPTION: Verilator output: Model implementation (design independent parts) #include "Valu6.h" #include "Valu6__Syms.h" +#include "verilated_vcd_c.h" -//========== +//============================================================ +// Constructors + +Valu6::Valu6(VerilatedContext* _vcontextp__, const char* _vcname__) + : vlSymsp{new Valu6__Syms(_vcontextp__, _vcname__, this)} + , alu_op_i{vlSymsp->TOP.alu_op_i} + , alu_in_1{vlSymsp->TOP.alu_in_1} + , alu_in_2{vlSymsp->TOP.alu_in_2} + , alu_output{vlSymsp->TOP.alu_output} + , rootp{&(vlSymsp->TOP)} +{ +} + +Valu6::Valu6(const char* _vcname__) + : Valu6(nullptr, _vcname__) +{ +} + +//============================================================ +// Destructor + +Valu6::~Valu6() { + delete vlSymsp; +} + +//============================================================ +// Evaluation loop + +void Valu6___024root___eval_initial(Valu6___024root* vlSelf); +void Valu6___024root___eval_settle(Valu6___024root* vlSelf); +void Valu6___024root___eval(Valu6___024root* vlSelf); +#ifdef VL_DEBUG +void Valu6___024root___eval_debug_assertions(Valu6___024root* vlSelf); +#endif // VL_DEBUG +void Valu6___024root___final(Valu6___024root* vlSelf); + +static void _eval_initial_loop(Valu6__Syms* __restrict vlSymsp) { + vlSymsp->__Vm_didInit = true; + Valu6___024root___eval_initial(&(vlSymsp->TOP)); + // Evaluate till stable + vlSymsp->__Vm_activity = true; + do { + VL_DEBUG_IF(VL_DBG_MSGF("+ Initial loop\n");); + Valu6___024root___eval_settle(&(vlSymsp->TOP)); + Valu6___024root___eval(&(vlSymsp->TOP)); + } while (0); +} void Valu6::eval_step() { - VL_DEBUG_IF(VL_DBG_MSGF("+++++TOP Evaluate Valu6::eval\n"); ); - Valu6__Syms* __restrict vlSymsp = this->__VlSymsp; // Setup global symbol table - Valu6* const __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + VL_DEBUG_IF(VL_DBG_MSGF("+++++TOP Evaluate Valu6::eval_step\n"); ); #ifdef VL_DEBUG // Debug assertions - _eval_debug_assertions(); + Valu6___024root___eval_debug_assertions(&(vlSymsp->TOP)); #endif // VL_DEBUG // Initialize if (VL_UNLIKELY(!vlSymsp->__Vm_didInit)) _eval_initial_loop(vlSymsp); // Evaluate till stable - int __VclockLoop = 0; - QData __Vchange = 1; + vlSymsp->__Vm_activity = true; do { VL_DEBUG_IF(VL_DBG_MSGF("+ Clock loop\n");); - vlSymsp->__Vm_activity = true; - _eval(vlSymsp); - if (VL_UNLIKELY(++__VclockLoop > 100)) { - // About to fail, so enable debug to see what's not settling. - // Note you must run make with OPT=-DVL_DEBUG for debug prints. - int __Vsaved_debug = Verilated::debug(); - Verilated::debug(1); - __Vchange = _change_request(vlSymsp); - Verilated::debug(__Vsaved_debug); - VL_FATAL_MT("alu6.v", 6, "", - "Verilated model didn't converge\n" - "- See DIDNOTCONVERGE in the Verilator manual"); - } else { - __Vchange = _change_request(vlSymsp); - } - } while (VL_UNLIKELY(__Vchange)); + Valu6___024root___eval(&(vlSymsp->TOP)); + } while (0); + // Evaluate cleanup } -void Valu6::_eval_initial_loop(Valu6__Syms* __restrict vlSymsp) { - vlSymsp->__Vm_didInit = true; - _eval_initial(vlSymsp); - vlSymsp->__Vm_activity = true; - // Evaluate till stable - int __VclockLoop = 0; - QData __Vchange = 1; - do { - _eval_settle(vlSymsp); - _eval(vlSymsp); - if (VL_UNLIKELY(++__VclockLoop > 100)) { - // About to fail, so enable debug to see what's not settling. - // Note you must run make with OPT=-DVL_DEBUG for debug prints. - int __Vsaved_debug = Verilated::debug(); - Verilated::debug(1); - __Vchange = _change_request(vlSymsp); - Verilated::debug(__Vsaved_debug); - VL_FATAL_MT("alu6.v", 6, "", - "Verilated model didn't DC converge\n" - "- See DIDNOTCONVERGE in the Verilator manual"); - } else { - __Vchange = _change_request(vlSymsp); - } - } while (VL_UNLIKELY(__Vchange)); -} +//============================================================ +// Utilities -VL_INLINE_OPT void Valu6::_combo__TOP__1(Valu6__Syms* __restrict vlSymsp) { - VL_DEBUG_IF(VL_DBG_MSGF("+ Valu6::_combo__TOP__1\n"); ); - Valu6* const __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; - // Body - vlTOPp->alu6__DOT__sum = (vlTOPp->alu_in_1 + ((1U - & (((IData)(vlTOPp->alu_op_i) - >> 3U) - | (((IData)(vlTOPp->alu_op_i) - >> 1U) - & (~ (IData)(vlTOPp->alu_op_i))))) - ? - ((IData)(1U) - + - (~ vlTOPp->alu_in_2)) - : vlTOPp->alu_in_2)); - vlTOPp->alu_output = ((0U == (7U & (IData)(vlTOPp->alu_op_i))) - ? vlTOPp->alu6__DOT__sum - : ((4U == (7U & (IData)(vlTOPp->alu_op_i))) - ? (vlTOPp->alu_in_1 - ^ vlTOPp->alu_in_2) - : ((6U == (7U & (IData)(vlTOPp->alu_op_i))) - ? (vlTOPp->alu_in_1 - | vlTOPp->alu_in_2) - : ((7U == (7U & (IData)(vlTOPp->alu_op_i))) - ? (vlTOPp->alu_in_1 - & vlTOPp->alu_in_2) - : ((1U == (7U - & (IData)(vlTOPp->alu_op_i))) - ? ((0x40U - & vlTOPp->alu_in_2) - ? 0U - : ((0x1fU - >= - (0x3fU - & vlTOPp->alu_in_2)) - ? - (vlTOPp->alu_in_1 - << - (0x3fU - & vlTOPp->alu_in_2)) - : 0U)) - : ((5U == - (7U - & (IData)(vlTOPp->alu_op_i))) - ? (( - (0x1fU - >= - (0x3fU - & vlTOPp->alu_in_2)) - ? - (vlTOPp->alu_in_1 - >> - (0x3fU - & vlTOPp->alu_in_2)) - : 0U) - | ((8U - & (IData)(vlTOPp->alu_op_i)) - ? - ((IData)(0xffffffffU) - << - ((0x80000000U - & vlTOPp->alu_in_2) - ? 0U - : - ((0x10U - & ((~ - (vlTOPp->alu_in_2 - >> 4U)) - << 4U)) - | ((8U - & ((~ - (vlTOPp->alu_in_2 - >> 3U)) - << 3U)) - | ((4U - & ((~ - (vlTOPp->alu_in_2 - >> 2U)) - << 2U)) - | ((2U - & ((~ - (vlTOPp->alu_in_2 - >> 1U)) - << 1U)) - | (1U - & (~ vlTOPp->alu_in_2)))))))) - : 0U)) - : ((2U - == - (7U - & (IData)(vlTOPp->alu_op_i))) - ? - (1U - & (vlTOPp->alu6__DOT__sum - >> 0x1fU)) - : - ((3U - == - (7U - & (IData)(vlTOPp->alu_op_i))) - ? - ((vlTOPp->alu_in_1 - < vlTOPp->alu_in_2) - ? 1U - : 0U) - : 0U)))))))); +VerilatedContext* Valu6::contextp() const { + return vlSymsp->_vm_contextp__; } -void Valu6::_eval(Valu6__Syms* __restrict vlSymsp) { - VL_DEBUG_IF(VL_DBG_MSGF("+ Valu6::_eval\n"); ); - Valu6* const __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; - // Body - vlTOPp->_combo__TOP__1(vlSymsp); +const char* Valu6::name() const { + return vlSymsp->name(); } -VL_INLINE_OPT QData Valu6::_change_request(Valu6__Syms* __restrict vlSymsp) { - VL_DEBUG_IF(VL_DBG_MSGF("+ Valu6::_change_request\n"); ); - Valu6* const __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; - // Body - return (vlTOPp->_change_request_1(vlSymsp)); +//============================================================ +// Invoke final blocks + +VL_ATTR_COLD void Valu6::final() { + Valu6___024root___final(&(vlSymsp->TOP)); } -VL_INLINE_OPT QData Valu6::_change_request_1(Valu6__Syms* __restrict vlSymsp) { - VL_DEBUG_IF(VL_DBG_MSGF("+ Valu6::_change_request_1\n"); ); - Valu6* const __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; - // Body - // Change detection - QData __req = false; // Logically a bool - return __req; +//============================================================ +// Trace configuration + +void Valu6___024root__trace_init_top(Valu6___024root* vlSelf, VerilatedVcd* tracep); + +VL_ATTR_COLD static void trace_init(void* voidSelf, VerilatedVcd* tracep, uint32_t code) { + // Callback from tracep->open() + Valu6___024root* const __restrict vlSelf VL_ATTR_UNUSED = static_cast<Valu6___024root*>(voidSelf); + Valu6__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp; + if (!vlSymsp->_vm_contextp__->calcUnusedSigs()) { + VL_FATAL_MT(__FILE__, __LINE__, __FILE__, + "Turning on wave traces requires Verilated::traceEverOn(true) call before time 0."); + } + vlSymsp->__Vm_baseCode = code; + tracep->scopeEscape(' '); + tracep->pushNamePrefix(std::string{vlSymsp->name()} + ' '); + Valu6___024root__trace_init_top(vlSelf, tracep); + tracep->popNamePrefix(); + tracep->scopeEscape('.'); } -#ifdef VL_DEBUG -void Valu6::_eval_debug_assertions() { - VL_DEBUG_IF(VL_DBG_MSGF("+ Valu6::_eval_debug_assertions\n"); ); - // Body - if (VL_UNLIKELY((alu_op_i & 0xf0U))) { - Verilated::overWidthError("alu_op_i");} +VL_ATTR_COLD void Valu6___024root__trace_register(Valu6___024root* vlSelf, VerilatedVcd* tracep); + +VL_ATTR_COLD void Valu6::trace(VerilatedVcdC* tfp, int levels, int options) { + if (false && levels && options) {} // Prevent unused + tfp->spTrace()->addInitCb(&trace_init, &(vlSymsp->TOP)); + Valu6___024root__trace_register(&(vlSymsp->TOP), tfp->spTrace()); } -#endif // VL_DEBUG diff --git a/verilog/alu/v6/obj_dir/Valu6.h b/verilog/alu/v6/obj_dir/Valu6.h index 9cddec9..b7d0b23 100644 --- a/verilog/alu/v6/obj_dir/Valu6.h +++ b/verilog/alu/v6/obj_dir/Valu6.h @@ -1,59 +1,56 @@ // Verilated -*- C++ -*- -// DESCRIPTION: Verilator output: Primary design header +// DESCRIPTION: Verilator output: Primary model header // // This header should be included by all source files instantiating the design. // The class here is then constructed to instantiate the design. // See the Verilator manual for examples. -#ifndef _VALU6_H_ -#define _VALU6_H_ // guard +#ifndef VERILATED_VALU6_H_ +#define VERILATED_VALU6_H_ // guard -#include "verilated_heavy.h" - -//========== +#include "verilated.h" class Valu6__Syms; -class Valu6_VerilatedVcd; - +class Valu6___024root; +class VerilatedVcdC; -//---------- +// This class is the main interface to the Verilated model +class Valu6 VL_NOT_FINAL { + private: + // Symbol table holding complete model state (owned by this class) + Valu6__Syms* const vlSymsp; -VL_MODULE(Valu6) { public: - + // PORTS // The application code writes and reads these signals to // propagate new values into/out from the Verilated model. - VL_IN8(alu_op_i,3,0); - VL_IN(alu_in_1,31,0); - VL_IN(alu_in_2,31,0); - VL_OUT(alu_output,31,0); - - // LOCAL SIGNALS - // Internals; generally not touched by application code - IData/*31:0*/ alu6__DOT__sum; - - // LOCAL VARIABLES - // Internals; generally not touched by application code - CData/*0:0*/ __Vm_traceActivity[1]; - - // INTERNAL VARIABLES - // Internals; generally not touched by application code - Valu6__Syms* __VlSymsp; // Symbol table - + VL_IN8(&alu_op_i,3,0); + VL_IN(&alu_in_1,31,0); + VL_IN(&alu_in_2,31,0); + VL_OUT(&alu_output,31,0); + + // CELLS + // Public to allow access to /* verilator public */ items. + // Otherwise the application code can consider these internals. + + // Root instance pointer to allow access to model internals, + // including inlined /* verilator public_flat_* */ items. + Valu6___024root* const rootp; + // CONSTRUCTORS - private: - VL_UNCOPYABLE(Valu6); ///< Copying not allowed - public: /// Construct the model; called by application code - /// The special name may be used to make a wrapper with a + /// If contextp is null, then the model will use the default global context + /// If name is "", then makes a wrapper with a /// single model invisible with respect to DPI scope names. - Valu6(const char* name = "TOP"); + explicit Valu6(VerilatedContext* contextp, const char* name = "TOP"); + explicit Valu6(const char* name = "TOP"); /// Destroy the model; called (often implicitly) by application code - ~Valu6(); - /// Trace signals in the model; called by application code - void trace(VerilatedVcdC* tfp, int levels, int options = 0); - + virtual ~Valu6(); + private: + VL_UNCOPYABLE(Valu6); ///< Copying not allowed + + public: // API METHODS /// Evaluate the model. Application must call when inputs change. void eval() { eval_step(); } @@ -64,39 +61,13 @@ VL_MODULE(Valu6) { void eval_end_step() {} /// Simulation complete, run final blocks. Application must call on completion. void final(); - - // INTERNAL METHODS - static void _eval_initial_loop(Valu6__Syms* __restrict vlSymsp); - void __Vconfigure(Valu6__Syms* symsp, bool first); - private: - static QData _change_request(Valu6__Syms* __restrict vlSymsp); - static QData _change_request_1(Valu6__Syms* __restrict vlSymsp); - public: - static void _combo__TOP__1(Valu6__Syms* __restrict vlSymsp); - private: - void _ctor_var_reset() VL_ATTR_COLD; - public: - static void _eval(Valu6__Syms* __restrict vlSymsp); - private: -#ifdef VL_DEBUG - void _eval_debug_assertions(); -#endif // VL_DEBUG - public: - static void _eval_initial(Valu6__Syms* __restrict vlSymsp) VL_ATTR_COLD; - static void _eval_settle(Valu6__Syms* __restrict vlSymsp) VL_ATTR_COLD; - private: - static void traceChgSub0(void* userp, VerilatedVcd* tracep); - static void traceChgTop0(void* userp, VerilatedVcd* tracep); - static void traceCleanup(void* userp, VerilatedVcd* /*unused*/); - static void traceFullSub0(void* userp, VerilatedVcd* tracep) VL_ATTR_COLD; - static void traceFullTop0(void* userp, VerilatedVcd* tracep) VL_ATTR_COLD; - static void traceInitSub0(void* userp, VerilatedVcd* tracep) VL_ATTR_COLD; - static void traceInitTop(void* userp, VerilatedVcd* tracep) VL_ATTR_COLD; - void traceRegister(VerilatedVcd* tracep) VL_ATTR_COLD; - static void traceInit(void* userp, VerilatedVcd* tracep, uint32_t code) VL_ATTR_COLD; + /// Trace signals in the model; called by application code + void trace(VerilatedVcdC* tfp, int levels, int options = 0); + /// Return current simulation context for this model. + /// Used to get to e.g. simulation time via contextp()->time() + VerilatedContext* contextp() const; + /// Retrieve name of this model instance (as passed to constructor). + const char* name() const; } VL_ATTR_ALIGNED(VL_CACHE_LINE_BYTES); -//---------- - - #endif // guard diff --git a/verilog/alu/v6/obj_dir/Valu6.mk b/verilog/alu/v6/obj_dir/Valu6.mk index d782d11..adf8ed7 100644 --- a/verilog/alu/v6/obj_dir/Valu6.mk +++ b/verilog/alu/v6/obj_dir/Valu6.mk @@ -17,6 +17,8 @@ SYSTEMC_INCLUDE ?= SYSTEMC_LIBDIR ?= ### Switches... +# C++ code coverage 0/1 (from --prof-c) +VM_PROFC = 0 # SystemC output mode? 0/1 (from --sc) VM_SC = 0 # Legacy or SystemC output mode? 0/1 (from --sc) diff --git a/verilog/alu/v6/obj_dir/Valu6__ALL.a b/verilog/alu/v6/obj_dir/Valu6__ALL.a Binary files differindex b05f397..22e235a 100644 --- a/verilog/alu/v6/obj_dir/Valu6__ALL.a +++ b/verilog/alu/v6/obj_dir/Valu6__ALL.a diff --git a/verilog/alu/v6/obj_dir/Valu6__ALL.o b/verilog/alu/v6/obj_dir/Valu6__ALL.o Binary files differindex 93f9ee6..d9eaf6c 100644 --- a/verilog/alu/v6/obj_dir/Valu6__ALL.o +++ b/verilog/alu/v6/obj_dir/Valu6__ALL.o diff --git a/verilog/alu/v6/obj_dir/Valu6__Slow.cpp b/verilog/alu/v6/obj_dir/Valu6__Slow.cpp deleted file mode 100644 index 6cd030d..0000000 --- a/verilog/alu/v6/obj_dir/Valu6__Slow.cpp +++ /dev/null @@ -1,61 +0,0 @@ -// Verilated -*- C++ -*- -// DESCRIPTION: Verilator output: Design implementation internals -// See Valu6.h for the primary calling header - -#include "Valu6.h" -#include "Valu6__Syms.h" - -//========== - -VL_CTOR_IMP(Valu6) { - Valu6__Syms* __restrict vlSymsp = __VlSymsp = new Valu6__Syms(this, name()); - Valu6* const __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; - // Reset internal values - - // Reset structure values - _ctor_var_reset(); -} - -void Valu6::__Vconfigure(Valu6__Syms* vlSymsp, bool first) { - if (false && first) {} // Prevent unused - this->__VlSymsp = vlSymsp; - if (false && this->__VlSymsp) {} // Prevent unused - Verilated::timeunit(-6); - Verilated::timeprecision(-9); -} - -Valu6::~Valu6() { - VL_DO_CLEAR(delete __VlSymsp, __VlSymsp = nullptr); -} - -void Valu6::_eval_initial(Valu6__Syms* __restrict vlSymsp) { - VL_DEBUG_IF(VL_DBG_MSGF("+ Valu6::_eval_initial\n"); ); - Valu6* const __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; -} - -void Valu6::final() { - VL_DEBUG_IF(VL_DBG_MSGF("+ Valu6::final\n"); ); - // Variables - Valu6__Syms* __restrict vlSymsp = this->__VlSymsp; - Valu6* const __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; -} - -void Valu6::_eval_settle(Valu6__Syms* __restrict vlSymsp) { - VL_DEBUG_IF(VL_DBG_MSGF("+ Valu6::_eval_settle\n"); ); - Valu6* const __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; - // Body - vlTOPp->_combo__TOP__1(vlSymsp); -} - -void Valu6::_ctor_var_reset() { - VL_DEBUG_IF(VL_DBG_MSGF("+ Valu6::_ctor_var_reset\n"); ); - // Body - alu_in_1 = VL_RAND_RESET_I(32); - alu_in_2 = VL_RAND_RESET_I(32); - alu_op_i = VL_RAND_RESET_I(4); - alu_output = VL_RAND_RESET_I(32); - alu6__DOT__sum = VL_RAND_RESET_I(32); - for (int __Vi0=0; __Vi0<1; ++__Vi0) { - __Vm_traceActivity[__Vi0] = VL_RAND_RESET_I(1); - } -} diff --git a/verilog/alu/v6/obj_dir/Valu6__Syms.cpp b/verilog/alu/v6/obj_dir/Valu6__Syms.cpp index c9b82af..fe8a162 100644 --- a/verilog/alu/v6/obj_dir/Valu6__Syms.cpp +++ b/verilog/alu/v6/obj_dir/Valu6__Syms.cpp @@ -3,25 +3,24 @@ #include "Valu6__Syms.h" #include "Valu6.h" - - +#include "Valu6___024root.h" // FUNCTIONS Valu6__Syms::~Valu6__Syms() { } -Valu6__Syms::Valu6__Syms(Valu6* topp, const char* namep) - // Setup locals - : __Vm_namep(namep) - , __Vm_activity(false) - , __Vm_baseCode(0) - , __Vm_didInit(false) - // Setup submodule names +Valu6__Syms::Valu6__Syms(VerilatedContext* contextp, const char* namep,Valu6* modelp) + : VerilatedSyms{contextp} + // Setup internal state of the Syms class + , __Vm_modelp{modelp} + // Setup module instances + , TOP{this, namep} { - // Pointer to top level - TOPp = topp; + // Configure time unit / time precision + _vm_contextp__->timeunit(-6); + _vm_contextp__->timeprecision(-9); // Setup each module's pointers to their submodules // Setup each module's pointer back to symbol table (for public functions) - TOPp->__Vconfigure(this, true); + TOP.__Vconfigure(true); } diff --git a/verilog/alu/v6/obj_dir/Valu6__Syms.h b/verilog/alu/v6/obj_dir/Valu6__Syms.h index dcbc3c1..7c4690b 100644 --- a/verilog/alu/v6/obj_dir/Valu6__Syms.h +++ b/verilog/alu/v6/obj_dir/Valu6__Syms.h @@ -4,34 +4,36 @@ // Internal details; most calling programs do not need this header, // unless using verilator public meta comments. -#ifndef _VALU6__SYMS_H_ -#define _VALU6__SYMS_H_ // guard +#ifndef VERILATED_VALU6__SYMS_H_ +#define VERILATED_VALU6__SYMS_H_ // guard -#include "verilated_heavy.h" +#include "verilated.h" + +// INCLUDE MODEL CLASS -// INCLUDE MODULE CLASSES #include "Valu6.h" -// SYMS CLASS -class Valu6__Syms : public VerilatedSyms { +// INCLUDE MODULE CLASSES +#include "Valu6___024root.h" + +// SYMS CLASS (contains all model state) +class Valu6__Syms final : public VerilatedSyms { public: - - // LOCAL STATE - const char* __Vm_namep; - bool __Vm_activity; ///< Used by trace routines to determine change occurred - uint32_t __Vm_baseCode; ///< Used by trace routines when tracing multiple models - bool __Vm_didInit; - - // SUBCELL STATE - Valu6* TOPp; - - // CREATORS - Valu6__Syms(Valu6* topp, const char* namep); + // INTERNAL STATE + Valu6* const __Vm_modelp; + bool __Vm_activity = false; ///< Used by trace routines to determine change occurred + uint32_t __Vm_baseCode = 0; ///< Used by trace routines when tracing multiple models + bool __Vm_didInit = false; + + // MODULE INSTANCE STATE + Valu6___024root TOP; + + // CONSTRUCTORS + Valu6__Syms(VerilatedContext* contextp, const char* namep, Valu6* modelp); ~Valu6__Syms(); - + // METHODS - inline const char* name() { return __Vm_namep; } - + const char* name() { return TOP.name(); } } VL_ATTR_ALIGNED(VL_CACHE_LINE_BYTES); #endif // guard diff --git a/verilog/alu/v6/obj_dir/Valu6__Trace.cpp b/verilog/alu/v6/obj_dir/Valu6__Trace.cpp deleted file mode 100644 index e2e3658..0000000 --- a/verilog/alu/v6/obj_dir/Valu6__Trace.cpp +++ /dev/null @@ -1,76 +0,0 @@ -// Verilated -*- C++ -*- -// DESCRIPTION: Verilator output: Tracing implementation internals -#include "verilated_vcd_c.h" -#include "Valu6__Syms.h" - - -void Valu6::traceChgTop0(void* userp, VerilatedVcd* tracep) { - Valu6__Syms* __restrict vlSymsp = static_cast<Valu6__Syms*>(userp); - Valu6* const __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; - // Variables - if (VL_UNLIKELY(!vlSymsp->__Vm_activity)) return; - // Body - { - vlTOPp->traceChgSub0(userp, tracep); - } -} - -void Valu6::traceChgSub0(void* userp, VerilatedVcd* tracep) { - Valu6__Syms* __restrict vlSymsp = static_cast<Valu6__Syms*>(userp); - Valu6* const __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; - vluint32_t* const oldp = tracep->oldp(vlSymsp->__Vm_baseCode + 1); - if (false && oldp) {} // Prevent unused - // Body - { - tracep->chgIData(oldp+0,(vlTOPp->alu_in_1),32); - tracep->chgIData(oldp+1,(vlTOPp->alu_in_2),32); - tracep->chgCData(oldp+2,(vlTOPp->alu_op_i),4); - tracep->chgIData(oldp+3,(vlTOPp->alu_output),32); - tracep->chgIData(oldp+4,(((IData)(1U) + (~ vlTOPp->alu_in_2))),32); - tracep->chgIData(oldp+5,(vlTOPp->alu6__DOT__sum),32); - tracep->chgIData(oldp+6,((((0x1fU >= (0x3fU - & vlTOPp->alu_in_2)) - ? (vlTOPp->alu_in_1 - >> (0x3fU & vlTOPp->alu_in_2)) - : 0U) | ((8U & (IData)(vlTOPp->alu_op_i)) - ? ((IData)(0xffffffffU) - << - ((0x80000000U - & vlTOPp->alu_in_2) - ? 0U - : - ((0x10U - & ((~ - (vlTOPp->alu_in_2 - >> 4U)) - << 4U)) - | ((8U - & ((~ - (vlTOPp->alu_in_2 - >> 3U)) - << 3U)) - | ((4U - & ((~ - (vlTOPp->alu_in_2 - >> 2U)) - << 2U)) - | ((2U - & ((~ - (vlTOPp->alu_in_2 - >> 1U)) - << 1U)) - | (1U - & (~ vlTOPp->alu_in_2)))))))) - : 0U))),32); - } -} - -void Valu6::traceCleanup(void* userp, VerilatedVcd* /*unused*/) { - Valu6__Syms* __restrict vlSymsp = static_cast<Valu6__Syms*>(userp); - Valu6* const __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; - // Body - { - vlSymsp->__Vm_activity = false; - vlTOPp->__Vm_traceActivity[0U] = 0U; - } -} diff --git a/verilog/alu/v6/obj_dir/Valu6__Trace__0.cpp b/verilog/alu/v6/obj_dir/Valu6__Trace__0.cpp index b2933ac..71768c8 100644 --- a/verilog/alu/v6/obj_dir/Valu6__Trace__0.cpp +++ b/verilog/alu/v6/obj_dir/Valu6__Trace__0.cpp @@ -21,17 +21,15 @@ void Valu6___024root__trace_chg_sub_0(Valu6___024root* vlSelf, VerilatedVcd* tra Valu6__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp; VL_DEBUG_IF(VL_DBG_MSGF("+ Valu6___024root__trace_chg_sub_0\n"); ); // Init - vluint32_t* const oldp VL_ATTR_UNUSED = tracep->oldp(vlSymsp->__Vm_baseCode + 1); + uint32_t* const oldp VL_ATTR_UNUSED = tracep->oldp(vlSymsp->__Vm_baseCode + 1); // Body tracep->chgIData(oldp+0,(vlSelf->alu_in_1),32); tracep->chgIData(oldp+1,(vlSelf->alu_in_2),32); tracep->chgCData(oldp+2,(vlSelf->alu_op_i),4); tracep->chgIData(oldp+3,(vlSelf->alu_output),32); - tracep->chgIData(oldp+4,(vlSelf->debugsum),32); - tracep->chgCData(oldp+5,(vlSelf->debugop),4); - tracep->chgIData(oldp+6,(((IData)(1U) + (~ vlSelf->alu_in_2))),32); - tracep->chgIData(oldp+7,(vlSelf->alu6__DOT__sum),32); - tracep->chgIData(oldp+8,((((0x1fU >= (0x3fU & vlSelf->alu_in_2)) + tracep->chgIData(oldp+4,(((IData)(1U) + (~ vlSelf->alu_in_2))),32); + tracep->chgIData(oldp+5,(vlSelf->alu6__DOT__sum),32); + tracep->chgIData(oldp+6,((((0x1fU >= (0x3fU & vlSelf->alu_in_2)) ? (vlSelf->alu_in_1 >> (0x3fU & vlSelf->alu_in_2)) : 0U) | ((8U & (IData)(vlSelf->alu_op_i)) diff --git a/verilog/alu/v6/obj_dir/Valu6__Trace__0__Slow.cpp b/verilog/alu/v6/obj_dir/Valu6__Trace__0__Slow.cpp index 83ce895..e16a25e 100644 --- a/verilog/alu/v6/obj_dir/Valu6__Trace__0__Slow.cpp +++ b/verilog/alu/v6/obj_dir/Valu6__Trace__0__Slow.cpp @@ -15,18 +15,14 @@ VL_ATTR_COLD void Valu6___024root__trace_init_sub__TOP__0(Valu6___024root* vlSel tracep->declBus(c+2,"alu_in_2", false,-1, 31,0); tracep->declBus(c+3,"alu_op_i", false,-1, 3,0); tracep->declBus(c+4,"alu_output", false,-1, 31,0); - tracep->declBus(c+5,"debugsum", false,-1, 31,0); - tracep->declBus(c+6,"debugop", false,-1, 3,0); tracep->pushNamePrefix("alu6 "); tracep->declBus(c+1,"alu_in_1", false,-1, 31,0); tracep->declBus(c+2,"alu_in_2", false,-1, 31,0); tracep->declBus(c+3,"alu_op_i", false,-1, 3,0); tracep->declBus(c+4,"alu_output", false,-1, 31,0); - tracep->declBus(c+5,"debugsum", false,-1, 31,0); - tracep->declBus(c+6,"debugop", false,-1, 3,0); - tracep->declBus(c+7,"complement2", false,-1, 31,0); - tracep->declBus(c+8,"sum", false,-1, 31,0); - tracep->declBus(c+9,"right", false,-1, 31,0); + tracep->declBus(c+5,"complement2", false,-1, 31,0); + tracep->declBus(c+6,"sum", false,-1, 31,0); + tracep->declBus(c+7,"right", false,-1, 31,0); tracep->popNamePrefix(1); } @@ -68,17 +64,15 @@ VL_ATTR_COLD void Valu6___024root__trace_full_sub_0(Valu6___024root* vlSelf, Ver Valu6__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp; VL_DEBUG_IF(VL_DBG_MSGF("+ Valu6___024root__trace_full_sub_0\n"); ); // Init - vluint32_t* const oldp VL_ATTR_UNUSED = tracep->oldp(vlSymsp->__Vm_baseCode); + uint32_t* const oldp VL_ATTR_UNUSED = tracep->oldp(vlSymsp->__Vm_baseCode); // Body tracep->fullIData(oldp+1,(vlSelf->alu_in_1),32); tracep->fullIData(oldp+2,(vlSelf->alu_in_2),32); tracep->fullCData(oldp+3,(vlSelf->alu_op_i),4); tracep->fullIData(oldp+4,(vlSelf->alu_output),32); - tracep->fullIData(oldp+5,(vlSelf->debugsum),32); - tracep->fullCData(oldp+6,(vlSelf->debugop),4); - tracep->fullIData(oldp+7,(((IData)(1U) + (~ vlSelf->alu_in_2))),32); - tracep->fullIData(oldp+8,(vlSelf->alu6__DOT__sum),32); - tracep->fullIData(oldp+9,((((0x1fU >= (0x3fU & vlSelf->alu_in_2)) + tracep->fullIData(oldp+5,(((IData)(1U) + (~ vlSelf->alu_in_2))),32); + tracep->fullIData(oldp+6,(vlSelf->alu6__DOT__sum),32); + tracep->fullIData(oldp+7,((((0x1fU >= (0x3fU & vlSelf->alu_in_2)) ? (vlSelf->alu_in_1 >> (0x3fU & vlSelf->alu_in_2)) : 0U) | ((8U & (IData)(vlSelf->alu_op_i)) diff --git a/verilog/alu/v6/obj_dir/Valu6__Trace__Slow.cpp b/verilog/alu/v6/obj_dir/Valu6__Trace__Slow.cpp deleted file mode 100644 index 89bdf46..0000000 --- a/verilog/alu/v6/obj_dir/Valu6__Trace__Slow.cpp +++ /dev/null @@ -1,127 +0,0 @@ -// Verilated -*- C++ -*- -// DESCRIPTION: Verilator output: Tracing implementation internals -#include "verilated_vcd_c.h" -#include "Valu6__Syms.h" - - -//====================== - -void Valu6::trace(VerilatedVcdC* tfp, int, int) { - tfp->spTrace()->addInitCb(&traceInit, __VlSymsp); - traceRegister(tfp->spTrace()); -} - -void Valu6::traceInit(void* userp, VerilatedVcd* tracep, uint32_t code) { - // Callback from tracep->open() - Valu6__Syms* __restrict vlSymsp = static_cast<Valu6__Syms*>(userp); - if (!Verilated::calcUnusedSigs()) { - VL_FATAL_MT(__FILE__, __LINE__, __FILE__, - "Turning on wave traces requires Verilated::traceEverOn(true) call before time 0."); - } - vlSymsp->__Vm_baseCode = code; - tracep->module(vlSymsp->name()); - tracep->scopeEscape(' '); - Valu6::traceInitTop(vlSymsp, tracep); - tracep->scopeEscape('.'); -} - -//====================== - - -void Valu6::traceInitTop(void* userp, VerilatedVcd* tracep) { - Valu6__Syms* __restrict vlSymsp = static_cast<Valu6__Syms*>(userp); - Valu6* const __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; - // Body - { - vlTOPp->traceInitSub0(userp, tracep); - } -} - -void Valu6::traceInitSub0(void* userp, VerilatedVcd* tracep) { - Valu6__Syms* __restrict vlSymsp = static_cast<Valu6__Syms*>(userp); - Valu6* const __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; - const int c = vlSymsp->__Vm_baseCode; - if (false && tracep && c) {} // Prevent unused - // Body - { - tracep->declBus(c+1,"alu_in_1", false,-1, 31,0); - tracep->declBus(c+2,"alu_in_2", false,-1, 31,0); - tracep->declBus(c+3,"alu_op_i", false,-1, 3,0); - tracep->declBus(c+4,"alu_output", false,-1, 31,0); - tracep->declBus(c+1,"alu6 alu_in_1", false,-1, 31,0); - tracep->declBus(c+2,"alu6 alu_in_2", false,-1, 31,0); - tracep->declBus(c+3,"alu6 alu_op_i", false,-1, 3,0); - tracep->declBus(c+4,"alu6 alu_output", false,-1, 31,0); - tracep->declBus(c+5,"alu6 complement2", false,-1, 31,0); - tracep->declBus(c+6,"alu6 sum", false,-1, 31,0); - tracep->declBus(c+7,"alu6 right", false,-1, 31,0); - } -} - -void Valu6::traceRegister(VerilatedVcd* tracep) { - // Body - { - tracep->addFullCb(&traceFullTop0, __VlSymsp); - tracep->addChgCb(&traceChgTop0, __VlSymsp); - tracep->addCleanupCb(&traceCleanup, __VlSymsp); - } -} - -void Valu6::traceFullTop0(void* userp, VerilatedVcd* tracep) { - Valu6__Syms* __restrict vlSymsp = static_cast<Valu6__Syms*>(userp); - Valu6* const __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; - // Body - { - vlTOPp->traceFullSub0(userp, tracep); - } -} - -void Valu6::traceFullSub0(void* userp, VerilatedVcd* tracep) { - Valu6__Syms* __restrict vlSymsp = static_cast<Valu6__Syms*>(userp); - Valu6* const __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; - vluint32_t* const oldp = tracep->oldp(vlSymsp->__Vm_baseCode); - if (false && oldp) {} // Prevent unused - // Body - { - tracep->fullIData(oldp+1,(vlTOPp->alu_in_1),32); - tracep->fullIData(oldp+2,(vlTOPp->alu_in_2),32); - tracep->fullCData(oldp+3,(vlTOPp->alu_op_i),4); - tracep->fullIData(oldp+4,(vlTOPp->alu_output),32); - tracep->fullIData(oldp+5,(((IData)(1U) + (~ vlTOPp->alu_in_2))),32); - tracep->fullIData(oldp+6,(vlTOPp->alu6__DOT__sum),32); - tracep->fullIData(oldp+7,((((0x1fU >= (0x3fU - & vlTOPp->alu_in_2)) - ? (vlTOPp->alu_in_1 - >> (0x3fU & vlTOPp->alu_in_2)) - : 0U) | ((8U & (IData)(vlTOPp->alu_op_i)) - ? ((IData)(0xffffffffU) - << - ((0x80000000U - & vlTOPp->alu_in_2) - ? 0U - : - ((0x10U - & ((~ - (vlTOPp->alu_in_2 - >> 4U)) - << 4U)) - | ((8U - & ((~ - (vlTOPp->alu_in_2 - >> 3U)) - << 3U)) - | ((4U - & ((~ - (vlTOPp->alu_in_2 - >> 2U)) - << 2U)) - | ((2U - & ((~ - (vlTOPp->alu_in_2 - >> 1U)) - << 1U)) - | (1U - & (~ vlTOPp->alu_in_2)))))))) - : 0U))),32); - } -} diff --git a/verilog/alu/v6/obj_dir/Valu6___024root.h b/verilog/alu/v6/obj_dir/Valu6___024root.h index f568bf9..968e6b6 100644 --- a/verilog/alu/v6/obj_dir/Valu6___024root.h +++ b/verilog/alu/v6/obj_dir/Valu6___024root.h @@ -13,23 +13,21 @@ VL_MODULE(Valu6___024root) { // DESIGN SPECIFIC STATE VL_IN8(alu_op_i,3,0); - VL_OUT8(debugop,3,0); VL_IN(alu_in_1,31,0); VL_IN(alu_in_2,31,0); VL_OUT(alu_output,31,0); - VL_OUT(debugsum,31,0); IData/*31:0*/ alu6__DOT__sum; // INTERNAL VARIABLES - Valu6__Syms* vlSymsp; // Symbol table + Valu6__Syms* const vlSymsp; // CONSTRUCTORS - Valu6___024root(const char* name); + Valu6___024root(Valu6__Syms* symsp, const char* name); ~Valu6___024root(); VL_UNCOPYABLE(Valu6___024root); // INTERNAL METHODS - void __Vconfigure(Valu6__Syms* symsp, bool first); + void __Vconfigure(bool first); } VL_ATTR_ALIGNED(VL_CACHE_LINE_BYTES); diff --git a/verilog/alu/v6/obj_dir/Valu6___024root__DepSet_he7565067__0.cpp b/verilog/alu/v6/obj_dir/Valu6___024root__DepSet_he7565067__0.cpp index afd43c4..4a9f08e 100644 --- a/verilog/alu/v6/obj_dir/Valu6___024root__DepSet_he7565067__0.cpp +++ b/verilog/alu/v6/obj_dir/Valu6___024root__DepSet_he7565067__0.cpp @@ -11,7 +11,6 @@ VL_INLINE_OPT void Valu6___024root___combo__TOP__0(Valu6___024root* vlSelf) { Valu6__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp; VL_DEBUG_IF(VL_DBG_MSGF("+ Valu6___024root___combo__TOP__0\n"); ); // Body - vlSelf->debugop = vlSelf->alu_op_i; vlSelf->alu6__DOT__sum = (vlSelf->alu_in_1 + ((IData)( (((IData)(vlSelf->alu_op_i) >> 3U) @@ -24,7 +23,6 @@ VL_INLINE_OPT void Valu6___024root___combo__TOP__0(Valu6___024root* vlSelf) { + (~ vlSelf->alu_in_2)) : vlSelf->alu_in_2)); - vlSelf->debugsum = vlSelf->alu6__DOT__sum; vlSelf->alu_output = ((0U == (7U & (IData)(vlSelf->alu_op_i))) ? vlSelf->alu6__DOT__sum : ((4U == (7U & (IData)(vlSelf->alu_op_i))) diff --git a/verilog/alu/v6/obj_dir/Valu6___024root__DepSet_he7565067__0__Slow.cpp b/verilog/alu/v6/obj_dir/Valu6___024root__DepSet_he7565067__0__Slow.cpp index 896483f..88991f6 100644 --- a/verilog/alu/v6/obj_dir/Valu6___024root__DepSet_he7565067__0__Slow.cpp +++ b/verilog/alu/v6/obj_dir/Valu6___024root__DepSet_he7565067__0__Slow.cpp @@ -37,7 +37,5 @@ VL_ATTR_COLD void Valu6___024root___ctor_var_reset(Valu6___024root* vlSelf) { vlSelf->alu_in_2 = VL_RAND_RESET_I(32); vlSelf->alu_op_i = VL_RAND_RESET_I(4); vlSelf->alu_output = VL_RAND_RESET_I(32); - vlSelf->debugsum = VL_RAND_RESET_I(32); - vlSelf->debugop = VL_RAND_RESET_I(4); vlSelf->alu6__DOT__sum = VL_RAND_RESET_I(32); } diff --git a/verilog/alu/v6/obj_dir/Valu6___024root__Slow.cpp b/verilog/alu/v6/obj_dir/Valu6___024root__Slow.cpp index 9918041..4167b09 100644 --- a/verilog/alu/v6/obj_dir/Valu6___024root__Slow.cpp +++ b/verilog/alu/v6/obj_dir/Valu6___024root__Slow.cpp @@ -9,16 +9,16 @@ void Valu6___024root___ctor_var_reset(Valu6___024root* vlSelf); -Valu6___024root::Valu6___024root(const char* _vcname__) - : VerilatedModule(_vcname__) +Valu6___024root::Valu6___024root(Valu6__Syms* symsp, const char* name) + : VerilatedModule{name} + , vlSymsp{symsp} { // Reset structure values Valu6___024root___ctor_var_reset(this); } -void Valu6___024root::__Vconfigure(Valu6__Syms* _vlSymsp, bool first) { +void Valu6___024root::__Vconfigure(bool first) { if (false && first) {} // Prevent unused - this->vlSymsp = _vlSymsp; } Valu6___024root::~Valu6___024root() { diff --git a/verilog/alu/v6/obj_dir/Valu6__ver.d b/verilog/alu/v6/obj_dir/Valu6__ver.d index 38bf8e0..6294dcb 100644 --- a/verilog/alu/v6/obj_dir/Valu6__ver.d +++ b/verilog/alu/v6/obj_dir/Valu6__ver.d @@ -1 +1 @@ -obj_dir/Valu6.cpp obj_dir/Valu6.h obj_dir/Valu6.mk obj_dir/Valu6__Slow.cpp obj_dir/Valu6__Syms.cpp obj_dir/Valu6__Syms.h obj_dir/Valu6__Trace.cpp obj_dir/Valu6__Trace__Slow.cpp obj_dir/Valu6__ver.d obj_dir/Valu6_classes.mk : /usr/bin/verilator_bin /usr/bin/verilator_bin alu6.v aluOp.vh +obj_dir/Valu6.cpp obj_dir/Valu6.h obj_dir/Valu6.mk obj_dir/Valu6__Syms.cpp obj_dir/Valu6__Syms.h obj_dir/Valu6__Trace__0.cpp obj_dir/Valu6__Trace__0__Slow.cpp obj_dir/Valu6___024root.h obj_dir/Valu6___024root__DepSet_he7565067__0.cpp obj_dir/Valu6___024root__DepSet_he7565067__0__Slow.cpp obj_dir/Valu6___024root__Slow.cpp obj_dir/Valu6__ver.d obj_dir/Valu6_classes.mk : /usr/bin/verilator_bin /usr/bin/verilator_bin alu6.v aluOp.vh diff --git a/verilog/alu/v6/obj_dir/Valu6__verFiles.dat b/verilog/alu/v6/obj_dir/Valu6__verFiles.dat index 389cc3d..2eb12ee 100644 --- a/verilog/alu/v6/obj_dir/Valu6__verFiles.dat +++ b/verilog/alu/v6/obj_dir/Valu6__verFiles.dat @@ -1,16 +1,19 @@ # DESCRIPTION: Verilator output: Timestamp data for --skip-identical. Delete at will. C "-Wall --cc --exe --build tbalu.cpp alu6.v --trace" -S 7544824 425500 1651977992 501242168 1627086909 0 "/usr/bin/verilator_bin" -S 982 195432 1652382291 705526780 1652382291 704526776 "alu6.v" -S 369 130885 1652206009 461809710 1652206009 461809710 "aluOp.vh" -T 10458 130865 1652382292 927532038 1652382292 927532038 "obj_dir/Valu6.cpp" -T 3600 130864 1652382292 927532038 1652382292 927532038 "obj_dir/Valu6.h" -T 1760 130873 1652382292 927532038 1652382292 927532038 "obj_dir/Valu6.mk" -T 1849 195436 1652382292 927532038 1652382292 927532038 "obj_dir/Valu6__Slow.cpp" -T 617 130862 1652382292 926532034 1652382292 926532034 "obj_dir/Valu6__Syms.cpp" -T 946 130863 1652382292 926532034 1652382292 926532034 "obj_dir/Valu6__Syms.h" -T 3801 195435 1652382292 927532038 1652382292 927532038 "obj_dir/Valu6__Trace.cpp" -T 5706 195434 1652382292 927532038 1652382292 927532038 "obj_dir/Valu6__Trace__Slow.cpp" -T 289 130861 1652382292 927532038 1652382292 927532038 "obj_dir/Valu6__ver.d" -T 0 0 1652382292 927532038 1652382292 927532038 "obj_dir/Valu6__verFiles.dat" -T 1641 130872 1652382292 927532038 1652382292 927532038 "obj_dir/Valu6_classes.mk" +S 8318248 12607448 1652499360 168084664 1652156559 0 "/usr/bin/verilator_bin" +S 982 10642998 1652590884 626885564 1652590884 626885564 "alu6.v" +S 369 10643000 1652590884 626885564 1652590884 626885564 "aluOp.vh" +T 3826 10643007 1652590925 168103129 1652590925 168103129 "obj_dir/Valu6.cpp" +T 2697 10643006 1652590925 168103129 1652590925 168103129 "obj_dir/Valu6.h" +T 1814 10643015 1652590925 168103129 1652590925 168103129 "obj_dir/Valu6.mk" +T 743 10643004 1652590925 168103129 1652590925 168103129 "obj_dir/Valu6__Syms.cpp" +T 1082 10643005 1652590925 168103129 1652590925 168103129 "obj_dir/Valu6__Syms.h" +T 4056 10643013 1652590925 168103129 1652590925 168103129 "obj_dir/Valu6__Trace__0.cpp" +T 5759 10643012 1652590925 168103129 1652590925 168103129 "obj_dir/Valu6__Trace__0__Slow.cpp" +T 785 10643008 1652590925 168103129 1652590925 168103129 "obj_dir/Valu6___024root.h" +T 7924 10643011 1652590925 168103129 1652590925 168103129 "obj_dir/Valu6___024root__DepSet_he7565067__0.cpp" +T 1639 10643010 1652590925 168103129 1652590925 168103129 "obj_dir/Valu6___024root__DepSet_he7565067__0__Slow.cpp" +T 620 10643009 1652590925 168103129 1652590925 168103129 "obj_dir/Valu6___024root__Slow.cpp" +T 435 10643016 1652590925 168103129 1652590925 168103129 "obj_dir/Valu6__ver.d" +T 0 0 1652590925 168103129 1652590925 168103129 "obj_dir/Valu6__verFiles.dat" +T 1743 10643014 1652590925 168103129 1652590925 168103129 "obj_dir/Valu6_classes.mk" diff --git a/verilog/alu/v6/obj_dir/Valu6_classes.mk b/verilog/alu/v6/obj_dir/Valu6_classes.mk index e08ed68..6ef8f77 100644 --- a/verilog/alu/v6/obj_dir/Valu6_classes.mk +++ b/verilog/alu/v6/obj_dir/Valu6_classes.mk @@ -26,19 +26,21 @@ VM_TRACE_FST_WRITER_THREAD = 0 # Generated module classes, fast-path, compile with highest optimization VM_CLASSES_FAST += \ Valu6 \ + Valu6___024root__DepSet_he7565067__0 \ # Generated module classes, non-fast-path, compile with low/medium optimization VM_CLASSES_SLOW += \ - Valu6__Slow \ + Valu6___024root__Slow \ + Valu6___024root__DepSet_he7565067__0__Slow \ # Generated support classes, fast-path, compile with highest optimization VM_SUPPORT_FAST += \ - Valu6__Trace \ + Valu6__Trace__0 \ # Generated support classes, non-fast-path, compile with low/medium optimization VM_SUPPORT_SLOW += \ Valu6__Syms \ - Valu6__Trace__Slow \ + Valu6__Trace__0__Slow \ # Global classes, need linked once per executable, fast-path, compile with highest optimization VM_GLOBAL_FAST += \ diff --git a/verilog/alu/v6/obj_dir/tbalu.o b/verilog/alu/v6/obj_dir/tbalu.o Binary files differindex f612394..16e8370 100644 --- a/verilog/alu/v6/obj_dir/tbalu.o +++ b/verilog/alu/v6/obj_dir/tbalu.o diff --git a/verilog/alu/v6/obj_dir/verilated.o b/verilog/alu/v6/obj_dir/verilated.o Binary files differindex a226a8b..a6100ef 100644 --- a/verilog/alu/v6/obj_dir/verilated.o +++ b/verilog/alu/v6/obj_dir/verilated.o diff --git a/verilog/alu/v6/obj_dir/verilated_vcd_c.o b/verilog/alu/v6/obj_dir/verilated_vcd_c.o Binary files differindex 469c75e..a454467 100644 --- a/verilog/alu/v6/obj_dir/verilated_vcd_c.o +++ b/verilog/alu/v6/obj_dir/verilated_vcd_c.o diff --git a/verilog/alu/v6/out b/verilog/alu/v6/out index 0337062..162c0f0 100644 --- a/verilog/alu/v6/out +++ b/verilog/alu/v6/out @@ -1,1200 +1,400 @@ SRA: -10 >>A -10 = -1 -00000000000000000000000000000000 -1101 SRA: -10 >>A -9 = -1 -11111111111111111111111111111111 -1101 SRA: -10 >>A -8 = -1 -11111111111111111111111111111110 -1101 SRA: -10 >>A -7 = -1 -11111111111111111111111111111101 -1101 SRA: -10 >>A -6 = -1 -11111111111111111111111111111100 -1101 SRA: -10 >>A -5 = -1 -11111111111111111111111111111011 -1101 SRA: -10 >>A -4 = -1 -11111111111111111111111111111010 -1101 SRA: -10 >>A -3 = -1 -11111111111111111111111111111001 -1101 SRA: -10 >>A -2 = -1 -11111111111111111111111111111000 -1101 SRA: -10 >>A -1 = -1 -11111111111111111111111111110111 -1101 SRA: -10 >>A 0 = -10 -11111111111111111111111111110110 -1101 SRA: -10 >>A 1 = -5 -11111111111111111111111111110101 -1101 SRA: -10 >>A 2 = -3 -11111111111111111111111111110100 -1101 SRA: -10 >>A 3 = -2 -11111111111111111111111111110011 -1101 SRA: -10 >>A 4 = -1 -11111111111111111111111111110010 -1101 SRA: -10 >>A 5 = -1 -11111111111111111111111111110001 -1101 SRA: -10 >>A 6 = -1 -11111111111111111111111111110000 -1101 SRA: -10 >>A 7 = -1 -11111111111111111111111111101111 -1101 SRA: -10 >>A 8 = -1 -11111111111111111111111111101110 -1101 SRA: -10 >>A 9 = -1 -11111111111111111111111111101101 -1101 SRA: -9 >>A -10 = -1 -00000000000000000000000000000001 -1101 SRA: -9 >>A -9 = -1 -00000000000000000000000000000000 -1101 SRA: -9 >>A -8 = -1 -11111111111111111111111111111111 -1101 SRA: -9 >>A -7 = -1 -11111111111111111111111111111110 -1101 SRA: -9 >>A -6 = -1 -11111111111111111111111111111101 -1101 SRA: -9 >>A -5 = -1 -11111111111111111111111111111100 -1101 SRA: -9 >>A -4 = -1 -11111111111111111111111111111011 -1101 SRA: -9 >>A -3 = -1 -11111111111111111111111111111010 -1101 SRA: -9 >>A -2 = -1 -11111111111111111111111111111001 -1101 SRA: -9 >>A -1 = -1 -11111111111111111111111111111000 -1101 SRA: -9 >>A 0 = -9 -11111111111111111111111111110111 -1101 SRA: -9 >>A 1 = -5 -11111111111111111111111111110110 -1101 SRA: -9 >>A 2 = -3 -11111111111111111111111111110101 -1101 SRA: -9 >>A 3 = -2 -11111111111111111111111111110100 -1101 SRA: -9 >>A 4 = -1 -11111111111111111111111111110011 -1101 SRA: -9 >>A 5 = -1 -11111111111111111111111111110010 -1101 SRA: -9 >>A 6 = -1 -11111111111111111111111111110001 -1101 SRA: -9 >>A 7 = -1 -11111111111111111111111111110000 -1101 SRA: -9 >>A 8 = -1 -11111111111111111111111111101111 -1101 SRA: -9 >>A 9 = -1 -11111111111111111111111111101110 -1101 SRA: -8 >>A -10 = -1 -00000000000000000000000000000010 -1101 SRA: -8 >>A -9 = -1 -00000000000000000000000000000001 -1101 SRA: -8 >>A -8 = -1 -00000000000000000000000000000000 -1101 SRA: -8 >>A -7 = -1 -11111111111111111111111111111111 -1101 SRA: -8 >>A -6 = -1 -11111111111111111111111111111110 -1101 SRA: -8 >>A -5 = -1 -11111111111111111111111111111101 -1101 SRA: -8 >>A -4 = -1 -11111111111111111111111111111100 -1101 SRA: -8 >>A -3 = -1 -11111111111111111111111111111011 -1101 SRA: -8 >>A -2 = -1 -11111111111111111111111111111010 -1101 SRA: -8 >>A -1 = -1 -11111111111111111111111111111001 -1101 SRA: -8 >>A 0 = -8 -11111111111111111111111111111000 -1101 SRA: -8 >>A 1 = -4 -11111111111111111111111111110111 -1101 SRA: -8 >>A 2 = -2 -11111111111111111111111111110110 -1101 SRA: -8 >>A 3 = -1 -11111111111111111111111111110101 -1101 SRA: -8 >>A 4 = -1 -11111111111111111111111111110100 -1101 SRA: -8 >>A 5 = -1 -11111111111111111111111111110011 -1101 SRA: -8 >>A 6 = -1 -11111111111111111111111111110010 -1101 SRA: -8 >>A 7 = -1 -11111111111111111111111111110001 -1101 SRA: -8 >>A 8 = -1 -11111111111111111111111111110000 -1101 SRA: -8 >>A 9 = -1 -11111111111111111111111111101111 -1101 SRA: -7 >>A -10 = -1 -00000000000000000000000000000011 -1101 SRA: -7 >>A -9 = -1 -00000000000000000000000000000010 -1101 SRA: -7 >>A -8 = -1 -00000000000000000000000000000001 -1101 SRA: -7 >>A -7 = -1 -00000000000000000000000000000000 -1101 SRA: -7 >>A -6 = -1 -11111111111111111111111111111111 -1101 SRA: -7 >>A -5 = -1 -11111111111111111111111111111110 -1101 SRA: -7 >>A -4 = -1 -11111111111111111111111111111101 -1101 SRA: -7 >>A -3 = -1 -11111111111111111111111111111100 -1101 SRA: -7 >>A -2 = -1 -11111111111111111111111111111011 -1101 SRA: -7 >>A -1 = -1 -11111111111111111111111111111010 -1101 SRA: -7 >>A 0 = -7 -11111111111111111111111111111001 -1101 SRA: -7 >>A 1 = -4 -11111111111111111111111111111000 -1101 SRA: -7 >>A 2 = -2 -11111111111111111111111111110111 -1101 SRA: -7 >>A 3 = -1 -11111111111111111111111111110110 -1101 SRA: -7 >>A 4 = -1 -11111111111111111111111111110101 -1101 SRA: -7 >>A 5 = -1 -11111111111111111111111111110100 -1101 SRA: -7 >>A 6 = -1 -11111111111111111111111111110011 -1101 SRA: -7 >>A 7 = -1 -11111111111111111111111111110010 -1101 SRA: -7 >>A 8 = -1 -11111111111111111111111111110001 -1101 SRA: -7 >>A 9 = -1 -11111111111111111111111111110000 -1101 SRA: -6 >>A -10 = -1 -00000000000000000000000000000100 -1101 SRA: -6 >>A -9 = -1 -00000000000000000000000000000011 -1101 SRA: -6 >>A -8 = -1 -00000000000000000000000000000010 -1101 SRA: -6 >>A -7 = -1 -00000000000000000000000000000001 -1101 SRA: -6 >>A -6 = -1 -00000000000000000000000000000000 -1101 SRA: -6 >>A -5 = -1 -11111111111111111111111111111111 -1101 SRA: -6 >>A -4 = -1 -11111111111111111111111111111110 -1101 SRA: -6 >>A -3 = -1 -11111111111111111111111111111101 -1101 SRA: -6 >>A -2 = -1 -11111111111111111111111111111100 -1101 SRA: -6 >>A -1 = -1 -11111111111111111111111111111011 -1101 SRA: -6 >>A 0 = -6 -11111111111111111111111111111010 -1101 SRA: -6 >>A 1 = -3 -11111111111111111111111111111001 -1101 SRA: -6 >>A 2 = -2 -11111111111111111111111111111000 -1101 SRA: -6 >>A 3 = -1 -11111111111111111111111111110111 -1101 SRA: -6 >>A 4 = -1 -11111111111111111111111111110110 -1101 SRA: -6 >>A 5 = -1 -11111111111111111111111111110101 -1101 SRA: -6 >>A 6 = -1 -11111111111111111111111111110100 -1101 SRA: -6 >>A 7 = -1 -11111111111111111111111111110011 -1101 SRA: -6 >>A 8 = -1 -11111111111111111111111111110010 -1101 SRA: -6 >>A 9 = -1 -11111111111111111111111111110001 -1101 SRA: -5 >>A -10 = -1 -00000000000000000000000000000101 -1101 SRA: -5 >>A -9 = -1 -00000000000000000000000000000100 -1101 SRA: -5 >>A -8 = -1 -00000000000000000000000000000011 -1101 SRA: -5 >>A -7 = -1 -00000000000000000000000000000010 -1101 SRA: -5 >>A -6 = -1 -00000000000000000000000000000001 -1101 SRA: -5 >>A -5 = -1 -00000000000000000000000000000000 -1101 SRA: -5 >>A -4 = -1 -11111111111111111111111111111111 -1101 SRA: -5 >>A -3 = -1 -11111111111111111111111111111110 -1101 SRA: -5 >>A -2 = -1 -11111111111111111111111111111101 -1101 SRA: -5 >>A -1 = -1 -11111111111111111111111111111100 -1101 SRA: -5 >>A 0 = -5 -11111111111111111111111111111011 -1101 SRA: -5 >>A 1 = -3 -11111111111111111111111111111010 -1101 SRA: -5 >>A 2 = -2 -11111111111111111111111111111001 -1101 SRA: -5 >>A 3 = -1 -11111111111111111111111111111000 -1101 SRA: -5 >>A 4 = -1 -11111111111111111111111111110111 -1101 SRA: -5 >>A 5 = -1 -11111111111111111111111111110110 -1101 SRA: -5 >>A 6 = -1 -11111111111111111111111111110101 -1101 SRA: -5 >>A 7 = -1 -11111111111111111111111111110100 -1101 SRA: -5 >>A 8 = -1 -11111111111111111111111111110011 -1101 SRA: -5 >>A 9 = -1 -11111111111111111111111111110010 -1101 SRA: -4 >>A -10 = -1 -00000000000000000000000000000110 -1101 SRA: -4 >>A -9 = -1 -00000000000000000000000000000101 -1101 SRA: -4 >>A -8 = -1 -00000000000000000000000000000100 -1101 SRA: -4 >>A -7 = -1 -00000000000000000000000000000011 -1101 SRA: -4 >>A -6 = -1 -00000000000000000000000000000010 -1101 SRA: -4 >>A -5 = -1 -00000000000000000000000000000001 -1101 SRA: -4 >>A -4 = -1 -00000000000000000000000000000000 -1101 SRA: -4 >>A -3 = -1 -11111111111111111111111111111111 -1101 SRA: -4 >>A -2 = -1 -11111111111111111111111111111110 -1101 SRA: -4 >>A -1 = -1 -11111111111111111111111111111101 -1101 SRA: -4 >>A 0 = -4 -11111111111111111111111111111100 -1101 SRA: -4 >>A 1 = -2 -11111111111111111111111111111011 -1101 SRA: -4 >>A 2 = -1 -11111111111111111111111111111010 -1101 SRA: -4 >>A 3 = -1 -11111111111111111111111111111001 -1101 SRA: -4 >>A 4 = -1 -11111111111111111111111111111000 -1101 SRA: -4 >>A 5 = -1 -11111111111111111111111111110111 -1101 SRA: -4 >>A 6 = -1 -11111111111111111111111111110110 -1101 SRA: -4 >>A 7 = -1 -11111111111111111111111111110101 -1101 SRA: -4 >>A 8 = -1 -11111111111111111111111111110100 -1101 SRA: -4 >>A 9 = -1 -11111111111111111111111111110011 -1101 SRA: -3 >>A -10 = -1 -00000000000000000000000000000111 -1101 SRA: -3 >>A -9 = -1 -00000000000000000000000000000110 -1101 SRA: -3 >>A -8 = -1 -00000000000000000000000000000101 -1101 SRA: -3 >>A -7 = -1 -00000000000000000000000000000100 -1101 SRA: -3 >>A -6 = -1 -00000000000000000000000000000011 -1101 SRA: -3 >>A -5 = -1 -00000000000000000000000000000010 -1101 SRA: -3 >>A -4 = -1 -00000000000000000000000000000001 -1101 SRA: -3 >>A -3 = -1 -00000000000000000000000000000000 -1101 SRA: -3 >>A -2 = -1 -11111111111111111111111111111111 -1101 SRA: -3 >>A -1 = -1 -11111111111111111111111111111110 -1101 SRA: -3 >>A 0 = -3 -11111111111111111111111111111101 -1101 SRA: -3 >>A 1 = -2 -11111111111111111111111111111100 -1101 SRA: -3 >>A 2 = -1 -11111111111111111111111111111011 -1101 SRA: -3 >>A 3 = -1 -11111111111111111111111111111010 -1101 SRA: -3 >>A 4 = -1 -11111111111111111111111111111001 -1101 SRA: -3 >>A 5 = -1 -11111111111111111111111111111000 -1101 SRA: -3 >>A 6 = -1 -11111111111111111111111111110111 -1101 SRA: -3 >>A 7 = -1 -11111111111111111111111111110110 -1101 SRA: -3 >>A 8 = -1 -11111111111111111111111111110101 -1101 SRA: -3 >>A 9 = -1 -11111111111111111111111111110100 -1101 SRA: -2 >>A -10 = -1 -00000000000000000000000000001000 -1101 SRA: -2 >>A -9 = -1 -00000000000000000000000000000111 -1101 SRA: -2 >>A -8 = -1 -00000000000000000000000000000110 -1101 SRA: -2 >>A -7 = -1 -00000000000000000000000000000101 -1101 SRA: -2 >>A -6 = -1 -00000000000000000000000000000100 -1101 SRA: -2 >>A -5 = -1 -00000000000000000000000000000011 -1101 SRA: -2 >>A -4 = -1 -00000000000000000000000000000010 -1101 SRA: -2 >>A -3 = -1 -00000000000000000000000000000001 -1101 SRA: -2 >>A -2 = -1 -00000000000000000000000000000000 -1101 SRA: -2 >>A -1 = -1 -11111111111111111111111111111111 -1101 SRA: -2 >>A 0 = -2 -11111111111111111111111111111110 -1101 SRA: -2 >>A 1 = -1 -11111111111111111111111111111101 -1101 SRA: -2 >>A 2 = -1 -11111111111111111111111111111100 -1101 SRA: -2 >>A 3 = -1 -11111111111111111111111111111011 -1101 SRA: -2 >>A 4 = -1 -11111111111111111111111111111010 -1101 SRA: -2 >>A 5 = -1 -11111111111111111111111111111001 -1101 SRA: -2 >>A 6 = -1 -11111111111111111111111111111000 -1101 SRA: -2 >>A 7 = -1 -11111111111111111111111111110111 -1101 SRA: -2 >>A 8 = -1 -11111111111111111111111111110110 -1101 SRA: -2 >>A 9 = -1 -11111111111111111111111111110101 -1101 SRA: -1 >>A -10 = -1 -00000000000000000000000000001001 -1101 SRA: -1 >>A -9 = -1 -00000000000000000000000000001000 -1101 SRA: -1 >>A -8 = -1 -00000000000000000000000000000111 -1101 SRA: -1 >>A -7 = -1 -00000000000000000000000000000110 -1101 SRA: -1 >>A -6 = -1 -00000000000000000000000000000101 -1101 SRA: -1 >>A -5 = -1 -00000000000000000000000000000100 -1101 SRA: -1 >>A -4 = -1 -00000000000000000000000000000011 -1101 SRA: -1 >>A -3 = -1 -00000000000000000000000000000010 -1101 SRA: -1 >>A -2 = -1 -00000000000000000000000000000001 -1101 SRA: -1 >>A -1 = -1 -00000000000000000000000000000000 -1101 SRA: -1 >>A 0 = -1 -11111111111111111111111111111111 -1101 SRA: -1 >>A 1 = -1 -11111111111111111111111111111110 -1101 SRA: -1 >>A 2 = -1 -11111111111111111111111111111101 -1101 SRA: -1 >>A 3 = -1 -11111111111111111111111111111100 -1101 SRA: -1 >>A 4 = -1 -11111111111111111111111111111011 -1101 SRA: -1 >>A 5 = -1 -11111111111111111111111111111010 -1101 SRA: -1 >>A 6 = -1 -11111111111111111111111111111001 -1101 SRA: -1 >>A 7 = -1 -11111111111111111111111111111000 -1101 SRA: -1 >>A 8 = -1 -11111111111111111111111111110111 -1101 SRA: -1 >>A 9 = -1 -11111111111111111111111111110110 -1101 SRA: 0 >>A -10 = -1 -00000000000000000000000000001010 -1101 SRA: 0 >>A -9 = -1 -00000000000000000000000000001001 -1101 SRA: 0 >>A -8 = -1 -00000000000000000000000000001000 -1101 SRA: 0 >>A -7 = -1 -00000000000000000000000000000111 -1101 SRA: 0 >>A -6 = -1 -00000000000000000000000000000110 -1101 SRA: 0 >>A -5 = -1 -00000000000000000000000000000101 -1101 SRA: 0 >>A -4 = -1 -00000000000000000000000000000100 -1101 SRA: 0 >>A -3 = -1 -00000000000000000000000000000011 -1101 SRA: 0 >>A -2 = -1 -00000000000000000000000000000010 -1101 SRA: 0 >>A -1 = -1 -00000000000000000000000000000001 -1101 SRA: 0 >>A 0 = -2147483648 -00000000000000000000000000000000 -1101 SRA: 0 >>A 1 = -1073741824 -11111111111111111111111111111111 -1101 SRA: 0 >>A 2 = -536870912 -11111111111111111111111111111110 -1101 SRA: 0 >>A 3 = -268435456 -11111111111111111111111111111101 -1101 SRA: 0 >>A 4 = -134217728 -11111111111111111111111111111100 -1101 SRA: 0 >>A 5 = -67108864 -11111111111111111111111111111011 -1101 SRA: 0 >>A 6 = -33554432 -11111111111111111111111111111010 -1101 SRA: 0 >>A 7 = -16777216 -11111111111111111111111111111001 -1101 SRA: 0 >>A 8 = -8388608 -11111111111111111111111111111000 -1101 SRA: 0 >>A 9 = -4194304 -11111111111111111111111111110111 -1101 SRA: 1 >>A -10 = -1 -00000000000000000000000000001011 -1101 SRA: 1 >>A -9 = -1 -00000000000000000000000000001010 -1101 SRA: 1 >>A -8 = -1 -00000000000000000000000000001001 -1101 SRA: 1 >>A -7 = -1 -00000000000000000000000000001000 -1101 SRA: 1 >>A -6 = -1 -00000000000000000000000000000111 -1101 SRA: 1 >>A -5 = -1 -00000000000000000000000000000110 -1101 SRA: 1 >>A -4 = -1 -00000000000000000000000000000101 -1101 SRA: 1 >>A -3 = -1 -00000000000000000000000000000100 -1101 SRA: 1 >>A -2 = -1 -00000000000000000000000000000011 -1101 SRA: 1 >>A -1 = -1 -00000000000000000000000000000010 -1101 SRA: 1 >>A 0 = -2147483647 -00000000000000000000000000000001 -1101 SRA: 1 >>A 1 = -1073741824 -00000000000000000000000000000000 -1101 SRA: 1 >>A 2 = -536870912 -11111111111111111111111111111111 -1101 SRA: 1 >>A 3 = -268435456 -11111111111111111111111111111110 -1101 SRA: 1 >>A 4 = -134217728 -11111111111111111111111111111101 -1101 SRA: 1 >>A 5 = -67108864 -11111111111111111111111111111100 -1101 SRA: 1 >>A 6 = -33554432 -11111111111111111111111111111011 -1101 SRA: 1 >>A 7 = -16777216 -11111111111111111111111111111010 -1101 SRA: 1 >>A 8 = -8388608 -11111111111111111111111111111001 -1101 SRA: 1 >>A 9 = -4194304 -11111111111111111111111111111000 -1101 SRA: 2 >>A -10 = -1 -00000000000000000000000000001100 -1101 SRA: 2 >>A -9 = -1 -00000000000000000000000000001011 -1101 SRA: 2 >>A -8 = -1 -00000000000000000000000000001010 -1101 SRA: 2 >>A -7 = -1 -00000000000000000000000000001001 -1101 SRA: 2 >>A -6 = -1 -00000000000000000000000000001000 -1101 SRA: 2 >>A -5 = -1 -00000000000000000000000000000111 -1101 SRA: 2 >>A -4 = -1 -00000000000000000000000000000110 -1101 SRA: 2 >>A -3 = -1 -00000000000000000000000000000101 -1101 SRA: 2 >>A -2 = -1 -00000000000000000000000000000100 -1101 SRA: 2 >>A -1 = -1 -00000000000000000000000000000011 -1101 SRA: 2 >>A 0 = -2147483646 -00000000000000000000000000000010 -1101 SRA: 2 >>A 1 = -1073741823 -00000000000000000000000000000001 -1101 SRA: 2 >>A 2 = -536870912 -00000000000000000000000000000000 -1101 SRA: 2 >>A 3 = -268435456 -11111111111111111111111111111111 -1101 SRA: 2 >>A 4 = -134217728 -11111111111111111111111111111110 -1101 SRA: 2 >>A 5 = -67108864 -11111111111111111111111111111101 -1101 SRA: 2 >>A 6 = -33554432 -11111111111111111111111111111100 -1101 SRA: 2 >>A 7 = -16777216 -11111111111111111111111111111011 -1101 SRA: 2 >>A 8 = -8388608 -11111111111111111111111111111010 -1101 SRA: 2 >>A 9 = -4194304 -11111111111111111111111111111001 -1101 SRA: 3 >>A -10 = -1 -00000000000000000000000000001101 -1101 SRA: 3 >>A -9 = -1 -00000000000000000000000000001100 -1101 SRA: 3 >>A -8 = -1 -00000000000000000000000000001011 -1101 SRA: 3 >>A -7 = -1 -00000000000000000000000000001010 -1101 SRA: 3 >>A -6 = -1 -00000000000000000000000000001001 -1101 SRA: 3 >>A -5 = -1 -00000000000000000000000000001000 -1101 SRA: 3 >>A -4 = -1 -00000000000000000000000000000111 -1101 SRA: 3 >>A -3 = -1 -00000000000000000000000000000110 -1101 SRA: 3 >>A -2 = -1 -00000000000000000000000000000101 -1101 SRA: 3 >>A -1 = -1 -00000000000000000000000000000100 -1101 SRA: 3 >>A 0 = -2147483645 -00000000000000000000000000000011 -1101 SRA: 3 >>A 1 = -1073741823 -00000000000000000000000000000010 -1101 SRA: 3 >>A 2 = -536870912 -00000000000000000000000000000001 -1101 SRA: 3 >>A 3 = -268435456 -00000000000000000000000000000000 -1101 SRA: 3 >>A 4 = -134217728 -11111111111111111111111111111111 -1101 SRA: 3 >>A 5 = -67108864 -11111111111111111111111111111110 -1101 SRA: 3 >>A 6 = -33554432 -11111111111111111111111111111101 -1101 SRA: 3 >>A 7 = -16777216 -11111111111111111111111111111100 -1101 SRA: 3 >>A 8 = -8388608 -11111111111111111111111111111011 -1101 SRA: 3 >>A 9 = -4194304 -11111111111111111111111111111010 -1101 SRA: 4 >>A -10 = -1 -00000000000000000000000000001110 -1101 SRA: 4 >>A -9 = -1 -00000000000000000000000000001101 -1101 SRA: 4 >>A -8 = -1 -00000000000000000000000000001100 -1101 SRA: 4 >>A -7 = -1 -00000000000000000000000000001011 -1101 SRA: 4 >>A -6 = -1 -00000000000000000000000000001010 -1101 SRA: 4 >>A -5 = -1 -00000000000000000000000000001001 -1101 SRA: 4 >>A -4 = -1 -00000000000000000000000000001000 -1101 SRA: 4 >>A -3 = -1 -00000000000000000000000000000111 -1101 SRA: 4 >>A -2 = -1 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-1101 diff --git a/verilog/alu/v6/waveform.vcd b/verilog/alu/v6/waveform.vcd index 045e968..38c5080 100644 --- a/verilog/alu/v6/waveform.vcd +++ b/verilog/alu/v6/waveform.vcd @@ -1,5 +1,5 @@ $version Generated by VerilatedVcd $end -$date Sun Apr 24 19:01:39 2022 $end +$date Sun May 15 01:02:15 2022 $end $timescale 1ns $end $scope module TOP $end @@ -7,18 +7,14 @@ $timescale 1ns $end $var wire 32 $ alu_in_2 [31:0] $end $var wire 4 % alu_op_i [3:0] $end $var wire 32 & alu_output [31:0] $end - $var wire 4 ( debugop [3:0] $end - $var wire 32 ' debugsum [31:0] $end $scope module alu6 $end $var wire 32 # alu_in_1 [31:0] $end $var wire 32 $ alu_in_2 [31:0] $end $var wire 4 % alu_op_i [3:0] $end $var wire 32 & alu_output [31:0] $end - $var wire 32 ) complement2 [31:0] $end - $var wire 4 ( debugop [3:0] $end - $var wire 32 ' debugsum [31:0] $end - $var wire 32 + right [31:0] $end - $var wire 32 * sum [31:0] $end + $var wire 32 ' complement2 [31:0] $end + $var wire 32 ) right [31:0] $end + $var wire 32 ( sum [31:0] $end $upscope $end $upscope $end $enddefinitions $end @@ -29,2308 +25,1907 @@ b11111111111111111111111111110110 # b11111111111111111111111111110110 $ b1101 % b11111111111111111111111111111111 & -b00000000000000000000000000000000 ' -b1101 ( -b00000000000000000000000000001010 ) -b00000000000000000000000000000000 * -b11111111111111111111111111111111 + +b00000000000000000000000000001010 ' +b00000000000000000000000000000000 ( +b11111111111111111111111111111111 ) #2 b11111111111111111111111111110111 $ -b11111111111111111111111111111111 ' -b00000000000000000000000000001001 ) -b11111111111111111111111111111111 * +b00000000000000000000000000001001 ' +b11111111111111111111111111111111 ( #3 b11111111111111111111111111111000 $ -b11111111111111111111111111111110 ' -b00000000000000000000000000001000 ) -b11111111111111111111111111111110 * +b00000000000000000000000000001000 ' +b11111111111111111111111111111110 ( #4 b11111111111111111111111111111001 $ -b11111111111111111111111111111101 ' -b00000000000000000000000000000111 ) -b11111111111111111111111111111101 * +b00000000000000000000000000000111 ' +b11111111111111111111111111111101 ( #5 b11111111111111111111111111111010 $ -b11111111111111111111111111111100 ' -b00000000000000000000000000000110 ) -b11111111111111111111111111111100 * +b00000000000000000000000000000110 ' +b11111111111111111111111111111100 ( #6 b11111111111111111111111111111011 $ -b11111111111111111111111111111011 ' -b00000000000000000000000000000101 ) -b11111111111111111111111111111011 * +b00000000000000000000000000000101 ' +b11111111111111111111111111111011 ( #7 b11111111111111111111111111111100 $ -b11111111111111111111111111111010 ' -b00000000000000000000000000000100 ) -b11111111111111111111111111111010 * +b00000000000000000000000000000100 ' +b11111111111111111111111111111010 ( #8 b11111111111111111111111111111101 $ -b11111111111111111111111111111001 ' -b00000000000000000000000000000011 ) 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